Clock Generators for SOC Processors

Clock Generators for SOC Processors

AngličtinaMäkká väzbaTlač na objednávku
Fahim Amr
Springer-Verlag New York Inc.
EAN: 9781441954701
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Podrobné informácie

This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.
EAN 9781441954701
ISBN 1441954708
Typ produktu Mäkká väzba
Vydavateľ Springer-Verlag New York Inc.
Dátum vydania 5. novembra 2010
Stránky 246
Jazyk English
Rozmery 235 x 155
Krajina United States
Čitatelia Professional & Scholarly
Autori Fahim Amr
Ilustrácie XVIII, 246 p. 213 illus.
Edícia Softcover reprint of hardcover 1st ed. 2005